<html>
<head><meta charset="utf-8"><title>Cool permutations · project-portable-simd · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/index.html">project-portable-simd</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html">Cool permutations</a></h3>

<hr>

<base href="https://rust-lang.zulipchat.com">

<head><link href="https://rust-lang.github.io/zulip_archive/style.css" rel="stylesheet"></head>

<a name="212598357"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212598357" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212598357">(Oct 07 2020 at 18:18)</a>:</h4>
<p>Vector permutations seem to be where arches go all-out in having very specific versions of these, for instance PowerISA's dynamic byte permutation:</p>
<blockquote>
<p>Version 3.0 B Power ISA™<br>
6.8.4<br>
Vector Permute Instruction<br>
The Vector Permute instruction allows any byte in two source Vector Registers to be copied to any byte in the target Vector Register. The bytes in a third source Vector Register specify from which byte in the first two source Vector Registers the  corresponding  target  byte  is  to  be  copied.  The  contents  of  the  third  source  Vector  Register are sometimes referred to as the “permute control vector”.</p>
</blockquote>



<a name="212599100"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212599100" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212599100">(Oct 07 2020 at 18:24)</a>:</h4>
<p>And Neon's TBL/TBX accepting 1-4 vectors and an index:</p>
<blockquote>
<p>VTBL, VTBX: Table and Table Extend</p>
<p>VTBL constructs a new vector from a table of vectors and an index vector. It is a byte-wise table lookup operation.</p>
<p>The table consists of one to four adjacent D registers. Each byte in the index vector is used to index a byte in the table of vectors. The indexed value is inserted into the result vector at the position corresponding to the location of the original index in the index vector.</p>
</blockquote>
<p><a href="/user_uploads/4715/aY_GysqA8ENtLi_p4J44Ngow/tbl.png">tbl.png</a></p>
<div class="message_inline_image"><a href="/user_uploads/4715/aY_GysqA8ENtLi_p4J44Ngow/tbl.png" title="tbl.png"><img src="/user_uploads/4715/aY_GysqA8ENtLi_p4J44Ngow/tbl.png"></a></div>



<a name="212601115"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212601115" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Thom Chiovoloni <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212601115">(Oct 07 2020 at 18:39)</a>:</h4>
<p>yeah. AMD tried to add that kind of powerful permute (<code>vpperm</code>) instruction in (what would have been) SSE5. it was supported (part of the XOP isa) for a while but intel never implemented it so they gave up it's not in new AMD chips</p>



<a name="212601258"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212601258" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212601258">(Oct 07 2020 at 18:40)</a>:</h4>
<p>alas. RIP SSE5.</p>



<a name="212601377"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212601377" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Caleb Zulawski <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212601377">(Oct 07 2020 at 18:41)</a>:</h4>
<p>I think MIPS has a permute like that too</p>



<a name="212601525"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212601525" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Thom Chiovoloni <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212601525">(Oct 07 2020 at 18:42)</a>:</h4>
<p>that said i think this sort of operation fits pretty well for leveraging the compiler at least.</p>



<a name="212685406"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212685406" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jonathan Bradbury <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212685406">(Oct 08 2020 at 13:03)</a>:</h4>
<p>s390x has the same permute as PowerISA/Altivec</p>



<a name="212728831"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/212728831" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#212728831">(Oct 08 2020 at 18:09)</a>:</h4>
<p>Oh cool! I didn't actually know that s390x has a vector ISA. Is it just part of the core ISA, and not a distinct feature?</p>



<a name="213940140"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Cool%20permutations/near/213940140" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jonathan Bradbury <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Cool.20permutations.html#213940140">(Oct 20 2020 at 15:59)</a>:</h4>
<p>It is now part of the base ISA as of z13.  Back in the 90's there was an old optional vector processor on the mainframe but that was more traditional Cray like vectors.   The latest z15 ISA documentation can be obtained here: <a href="http://publibfp.dhe.ibm.com/epubs/pdf/a227832c.pdf">http://publibfp.dhe.ibm.com/epubs/pdf/a227832c.pdf</a>   (See chapters 21-25)</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
</html>